Erasing a block (e.g., a grouping of cells, such as those cells located between sense circuitry of a memory device) of cells in a memory device is typically performed by selecting a particular block to erase. For the block to be erased, an access line, such as those typically referred to as word lines, have a bias of 0 volts applied thereto, and high voltage pulses are applied to the entire substrate. To inhibit programming on non-selected blocks, the word lines of the non-selected blocks have a high voltage applied thereto, so there is a small or zero potential difference between the word lines and the substrate. Since there is a significant potential difference between word lines on selected blocks and the substrate, those cells are erased.
Typically, a series of erase pulses of increasing magnitude are applied to the selected block, as not all cells erase at the same rate, e.g., with the same erase pulse. After each erase pulse, a verification sequence is performed to verify the level to which cells on the selected erase block are erased. In a multiple level cell, it is often desired to erase to an erase voltage of less than −3 volts, for example. Since some cells erase faster than others, successive erase pulses can over-erase cells to a voltage substantially less than the desired erase voltage, in some cases erasing cells to as low as −7 volts, for example.
In multiple level cell memories, where the number of potential data states (e.g., representing a number of bits) per cell are increasing, cell disturb can become a large issue. If cells are erased to substantially lower than the typical erase voltage, then upon programming those over-erased cells, a jump in voltage for a cell to be programmed can require programming a cell from, for example, −7 volts all the way to, for example, +4 volts or more. In a situation such as this, there are many potential coupling issues between the cell being programmed and adjacent cells, horizontally, vertically, and diagonally. The greater the movement in voltage between an erased cell and its programmed potential, the worse the potential coupling issues.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing erase distributions in memories, for example.